Memory is a crucial part of most typical computers. Most memories, especially dynamic random access memories (RAMs), use relatively complex bus protocols for communication. Most memory designs also assume that the memory will be connected directly to exactly one host (e.g., a “North Bridge”). All writes come from that host, and data from all reads go to that host. If more than one destination for data is possible, logic at some higher level must determine the destination for the data, and send that data to the appropriate destination.
This complex protocol and limitation to a single host connection limit flexibility in using memory. These limitations become particularly apparent when using memory in a network on a chip processing device.